下面程序是参数可定制带计数使能异步复位计数器的 VHDL 描述,试补充完整。 -- N-bit Up Counter with Load, Count Enable, and -- AsynchronousReset library ieee; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; entity counter_n is _____ (width : integer:= 8); port(data : in std_logic_vector(width-1 downto 0); load, en, clk,rst : in std_logic; q : out std_logic_vector(______downto 0)); end counter_n; architecture behave of counter_n is signal count : std_logic_vector(width-1 downto 0); begin process(clk, rst) begin if rst = '1'then count<= (_______) ; ―― 清零 elsif______then ―― 边沿检测 if load= '1' then count<= data; elsifen = '1' then count<= count + 1; endif; end if; end process; _________ ; end behave;